Citation
Abstract
The Big Viterbi Decoder (BVD) is a powerful new error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and CRAF/ Cassini missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols though a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane. A new “single-board” BVD is being constructed now for implementation in DSN stations. The design is based upon a new VLSI chip which contains 65,536 bits of static RAM and circuitry now located on boards and in 4 gate arrays. Sixtyfour of these new chips will be mounted on a single board and interconnected with 5120 wires. Experience gained from the prototype actually led to special circuitry designed inside the chips for simpler and better checking of these wires. Furthermore, each chip also operates independently as a complete, constraint length 9, rate 1/6—(9,1/6) Viterbi decoder, for testing within the single-board BVD. Like the prototype BVD, the new decoder can also be programmed to decode convolutional codes having constraint length 2 to 15 and rate 1/2, 1/3, 1/4, 1/5, or 1/6.
Details
- Volume
- 42-106
- Published
- August 15, 1991
- Pages
- 175–182
- File Size
- 652.5 KB