Citation
Abstract
This article provides an overview of the communications system that is being developed as part of the Micro Communications and Avionics Systems (MCAS). The first phase (MCAS1) effort is being focused on a digital binary phase-shift-key (BPSK) system with both suppressed- and residual-carrier capabilities. The system is being designed to operate over a wide range of data rates from 1 kb/s to 4 Mb/s and must accommodate frequency uncertainties up to 10 kHz with navigational Doppler tracking capabilities. As such, the design is highly programmable and incorporates efficient front-end digital decimation architectures to minimize power consumption requirements. The MCAS1 design uses field programmable gate array (FPGA) technology to prototype the real-time MCAS1 communications system. Ultimately, this design will migrate to a radiation-hardened, application-specific integrated circuit (ASIC). Specific emphasis in this article is focused on the digital front end and BPSK demodulation portions of the MCAS1 receiver.
Keywords
Details
- Volume
- 42-138
- Published
- August 15, 1999
- Pages
- 1–35
- File Size
- 973.9 KB