Citation
Abstract
We describe the architecture and algorithm development for a field programmable gate array (FPGA) wideband telemetry receiver prototype capable of processing data rates in excess of 100 megabits per second (Mbps). The high-speed parallel implementations of the matched filter, carrier phase tracking loop, and symbol timing recovery loop are discussed, along with simulation and hardware performance results.
Details
- Volume
- 42-166
- Published
- August 15, 2006
- Pages
- 1–23
- File Size
- 242.7 KB