Citation
Abstract
The National Aeronautics and Space Administration has developed a capacityapproaching modulation and coding scheme that comprises a serial concatenation of an inner accumulate pulse-position modulation and an outer convolutional code for deep-space optical communications. Decoding of this serially concatenated pulseposition modulation (SCPPM) code uses a turbo-like algorithm. However, the inner code trellis contains many parallel edges that are not typical in standard turbo codes and, therefore, a straightforward application of classical turbo decoding is very inefficient. Here, we present various optimizations applicable in hardware implementation of the SCPPM decoder. More specifically, we feature a Super Gamma computation to efficiently handle parallel trellis edges, a “maxstar top 2” circuit fit for pipelining, a modified two’s complement subtraction circuit with a shorter path delay, and a cyclic redundancy check circuit for window-based turbo decoders. We also present a polynomial interleaver where current interleaver positions can be calculated from previous positions. This recursive interleaver property enables an algorithmic realization in which no memory is needed to store the interleaver mappings. Using the featured optimizations, we implement a 6.72 megabits-per-second (Mbps) SCPPM decoder on a single field-programmable gate array (FPGA). Compared to the current data rate of 256 kbps from Mars, the SCPPM-coded scheme represents a throughput increase of more than twenty-six fold. Extension to a 50-Mbps decoder on a board with multiple FPGAs follows naturally. We show through hardware simulations that the SCPPM-coded system can operate within 1 dB of the Shannon capacity at nominal operating conditions.
Details
- Volume
- 42-168
- Published
- February 15, 2007
- Pages
- 1–31
- File Size
- 261.5 KB