Citation
Abstract
This article describes a 4-bit and a 3-bit adder which can be implemented under special hardware restrictions. The chip to be used is Field-Programmable Logic Array (FPLA) with 12 input lines, 50 AND gates inside, and output through only 6 OR gates. The context in which it is being used requires an “enable” function which can suppress one of the two numbers to be added. The 3-bit enabled adder is compatible with lookahead-carry mechanizations using the 748182. It will be used in the accumulator for the RFI project.
Details
- Volume
- 42-46
- Published
- August 15, 1978
- Pages
- 76–80
- File Size
- 264.5 KB