Citation
Abstract
Two methods of processing two’s complement binary data are presented. They were used in the design of the High-Speed Front End of the Multimegabit Subsystem. The first method is for rounding with zero error in the mean and is useful when large numbers of rounded values are to be accumulated. The second method consists of attaching a “1” as a least significant bit to the output word of an A-D converter, thus processing it as an odd number with one more bit. This compensates for the negative bias that A-D converters have when their zero is set for symmetrical positive and negative output ranges as is customary. When used with emitter coupled logic circuits, these methods result in simpler logic design.
Details
- Volume
- 42-56
- Published
- April 15, 1980
- Pages
- 85–89
- File Size
- 338.8 KB