Citation
Abstract
This article describes a VLSI architecture and layout for a convolutional encoder. This architecture allows a single chip implementation of an encoder that is capable of handling. many different convolutional codes including all the convolutional codes that are presently used by NASA for deep space missions.
Details
- Volume
- 42-72
- Published
- February 15, 1983
- Pages
- 61–69
- File Size
- 602.7 KB