Citation
Abstract
This article describes a VLSI architecture and layout for an 8-bit finite field multiplier. The algorithm used in this design was developed by Massey and Omura (Ref. 1). A normal basis representation of finite field elements is used to reduce the multiplication complexity. It is shown in this article that a drastic improvement has been achieved in this design. This multiplier will be used intensively in the implementation of an 8-bit Reed-Solomon decoder and in many other related projects.
Details
- Volume
- 42-83
- Published
- November 15, 1985
- Pages
- 45–50
- File Size
- 357.7 KB