Citation
Abstract
This article describes a fully systolic architecture for the implementation of digital sequence correlator/accumulators. These devices consist of a two-dimensional array of processing elements that are conceived for efficient fabrication in Very Large Scale Integrated (VLSI) circuits. A custom VLSI chip that was implemented using these concepts is described. The chip, which contains a four-lag three-level sequence correlator and four bits of accumulation with overflow detection, was designed using the Integrated UNIXBased Computer Aided Design (CAD) System. Applications of such devices include the synchronization of coded telemetry data, alignment of both real time and non-real time Very Large Baseline Interferometry (VLBI) signals, and the implementation of digital filters and processors of many types.
Details
- Volume
- 42-85
- Published
- May 15, 1986
- Pages
- 62–68
- File Size
- 503.7 KB