Citation
Abstract
This article describes a new very-large-scale integration (VLSI) architecture for implementing Reed-Solomon (RS) decoders that can correct both errors and erasures. This new architecture implements a Reed-Solomon decoder by using replication of a single VLSI chip. It is anticipated that this single-chip-type RS decoder approach will save substantial development and production costs. It is estimated that reduction in cost by a factor of four is possible with this new architecture. decoder is programmable between 8-bit and 10-bit symbol sizes. Furthermore, this Reed-Solomon Therefore, both an 8-bit CCSDS RS decoder and a 10-bit decoder are obtained at the same time, and when concatenated with a (15,1/6) Viterbi decoder, provide an additional 2.1-dB coding gain.
Details
- Volume
- 42-96
- Published
- February 15, 1989
- Pages
- 40–48
- File Size
- 337.4 KB