Citation
Abstract
This article deals with the generation of test vectors and design-for-test aspects of the JPL VLSI Viterbi decoder chip. Each processor IC contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logic is tested exhaustively, Using this approach, no detailed logic design or fault model is required, All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults.
Details
- Volume
- 42-96
- Published
- February 15, 1989
- Pages
- 59–79
- File Size
- 546.3 KB