Citation
Abstract
We describe a hardware implementation of a state-of-the-art lossless image compression algorithm. The algorithm is based on the LOCO-I (low complexity lossless compression for images) algorithm developed by Weinberger, Seroussi, and Sapiro, with modifications to lower the implementation complexity. In this setup, the compression itself is performed entirely in hardware using a field programmable gate array and a small amount of random access memory. The compression speed achieved is 1.33 Mpixels/second. Our algorithm yields about 15 percent better compression than the Rice algorithm.
Keywords
lossless image compression
FPGA
LOCO
data compression
Details
- Volume
- 42-144
- Published
- February 15, 2001
- Pages
- 1–11
- File Size
- 276.7 KB